JPS6250862B2 - - Google Patents

Info

Publication number
JPS6250862B2
JPS6250862B2 JP54061623A JP6162379A JPS6250862B2 JP S6250862 B2 JPS6250862 B2 JP S6250862B2 JP 54061623 A JP54061623 A JP 54061623A JP 6162379 A JP6162379 A JP 6162379A JP S6250862 B2 JPS6250862 B2 JP S6250862B2
Authority
JP
Japan
Prior art keywords
bus
memory
subsystem
request message
message
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54061623A
Other languages
English (en)
Japanese (ja)
Other versions
JPS54152928A (en
Inventor
Sankaruchando Shaa Niranjan
Furedoritsuku Teiraa Jeemusu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Publication of JPS54152928A publication Critical patent/JPS54152928A/ja
Publication of JPS6250862B2 publication Critical patent/JPS6250862B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
  • Small-Scale Networks (AREA)
JP6162379A 1978-05-22 1979-05-21 Method of and system for calling memory on different buses Granted JPS54152928A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/908,183 US4205373A (en) 1978-05-22 1978-05-22 System and method for accessing memory connected to different bus and requesting subsystem

Publications (2)

Publication Number Publication Date
JPS54152928A JPS54152928A (en) 1979-12-01
JPS6250862B2 true JPS6250862B2 (en]) 1987-10-27

Family

ID=25425331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6162379A Granted JPS54152928A (en) 1978-05-22 1979-05-21 Method of and system for calling memory on different buses

Country Status (5)

Country Link
US (1) US4205373A (en])
JP (1) JPS54152928A (en])
DE (1) DE2920490C2 (en])
FR (1) FR2426937B1 (en])
GB (1) GB2021824B (en])

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4527237A (en) * 1979-10-11 1985-07-02 Nanodata Computer Corporation Data processing system
DE3006165C2 (de) 1980-02-19 1981-11-12 Siemens AG, 1000 Berlin und 8000 München Ankoppeleinrichtung zum Ankoppeln zweier Datenverarbeitungsanlagen
US5146572A (en) * 1980-11-17 1992-09-08 International Business Machines Corporation Multiple data format interface
US4520452A (en) * 1982-03-16 1985-05-28 Burroughs Corporation Memory selection in a multiple line adapter organization
WO1983003316A1 (en) * 1982-03-16 1983-09-29 Burroughs Corp Memory selection in a multiple line adapter organization
US4667305A (en) * 1982-06-30 1987-05-19 International Business Machines Corporation Circuits for accessing a variable width data bus with a variable width data field
US4751727A (en) * 1982-09-30 1988-06-14 American Telephone And Telegraph Company, At&T Bell Laboratories Multiprocessor computing system featuring shared global control
US4626634A (en) * 1982-09-30 1986-12-02 At&T Bell Laboratories Multiprocessor computing system featuring shared global control
US4713834A (en) * 1982-09-30 1987-12-15 American Telephone And Telegraph Company, At&T Bell Laboratories Multiprocessor computing system featuring shared global control
US4663729A (en) * 1984-06-01 1987-05-05 International Business Machines Corp. Display architecture having variable data width
US4766564A (en) * 1984-08-13 1988-08-23 International Business Machines Corporation Dual putaway/bypass busses for multiple arithmetic units
CA1239227A (en) * 1984-10-17 1988-07-12 Randy D. Pfeifer Method of and arrangement for ordering of multiprocessor operations in a multiprocessor system
US4768145A (en) * 1984-11-28 1988-08-30 Hewlett-Packard Company Bus system
US4787029A (en) * 1986-09-29 1988-11-22 Gte Communication Systems Corporation Level converting bus extender with subsystem selection signal decoding enabling connection to microprocessor
US4882727A (en) * 1987-03-11 1989-11-21 Aristacom International, Inc. Adaptive digital network interface
US4890254A (en) * 1987-03-11 1989-12-26 Aristacom International, Inc. Clock disabling circuit
US4958342A (en) * 1987-03-11 1990-09-18 Aristacom International, Inc. Adaptive digital network interface
US5029074A (en) * 1987-06-29 1991-07-02 Digital Equipment Corporation Bus adapter unit for digital processing system
US4935894A (en) * 1987-08-31 1990-06-19 Motorola, Inc. Multi-processor, multi-bus system with bus interface comprising FIFO register stocks for receiving and transmitting data and control information
GB2211326B (en) * 1987-10-16 1991-12-11 Hitachi Ltd Address bus control apparatus
US5093807A (en) * 1987-12-23 1992-03-03 Texas Instruments Incorporated Video frame storage system
US5587962A (en) * 1987-12-23 1996-12-24 Texas Instruments Incorporated Memory circuit accommodating both serial and random access including an alternate address buffer register
US5081576A (en) * 1988-03-24 1992-01-14 Encore Computer U.S., Inc. Advance polling bus arbiter for use in multiple bus system
US5138703A (en) * 1988-03-31 1992-08-11 Kabushiki Kaisha Toshiba Method of and apparatus for expanding system bus
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
EP0357075A3 (en) * 1988-09-02 1991-12-11 Fujitsu Limited Data control device and system using the same
US5191657A (en) * 1989-11-09 1993-03-02 Ast Research, Inc. Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
US5243703A (en) * 1990-04-18 1993-09-07 Rambus, Inc. Apparatus for synchronously generating clock signals in a data processing system
US6324120B2 (en) 1990-04-18 2001-11-27 Rambus Inc. Memory device having a variable data output length
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
EP1004956B2 (en) * 1990-04-18 2009-02-11 Rambus Inc. Method of operating a synchronous memory having a variable data output length
US5369748A (en) * 1991-08-23 1994-11-29 Nexgen Microsystems Bus arbitration in a dual-bus architecture where one bus has relatively high latency
US5341495A (en) * 1991-10-04 1994-08-23 Bull Hn Information Systems, Inc. Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols
JP3524110B2 (ja) * 1992-11-06 2004-05-10 株式会社ルネサステクノロジ マイクロコンピュータシステム
US5649127A (en) * 1994-05-04 1997-07-15 Samsung Semiconductor, Inc. Method and apparatus for packing digital data
US5905961A (en) * 1997-02-05 1999-05-18 Motorola, Inc. Method and apparatus for managing remote unit increased power transmission during location
US6185651B1 (en) * 1997-11-05 2001-02-06 Compaq Computer Corp SCSI bus extender utilizing tagged queuing in a multi-initiator environment
KR100261218B1 (ko) * 1997-12-08 2000-07-01 윤종용 반도체 메모리 장치의 핀 어사인먼트 방법 및 패킷 단위의 신호를 입력으로 하는 반도체 메모리장치
US6141710A (en) * 1998-12-15 2000-10-31 Daimlerchrysler Corporation Interfacing vehicle data bus to intelligent transportation system (ITS) data bus via a gateway module
US6658519B1 (en) * 2000-07-28 2003-12-02 International Business Machines Corporation Bus bridge with embedded input/output (I/O) and transaction tracing capabilities
US7013355B2 (en) * 2003-01-09 2006-03-14 Micrel, Incorporated Device and method for improved serial bus transaction using incremental address decode
US20070027485A1 (en) * 2005-07-29 2007-02-01 Kallmyer Todd A Implantable medical device bus system and method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3932841A (en) * 1973-10-26 1976-01-13 Raytheon Company Bus controller for digital computer system
US3940743A (en) * 1973-11-05 1976-02-24 Digital Equipment Corporation Interconnecting unit for independently operable data processing systems
US3890471A (en) * 1973-12-17 1975-06-17 Bell Telephone Labor Inc Loop data transmission arrangement employing an interloop communication terminal
US4041472A (en) * 1976-04-29 1977-08-09 Ncr Corporation Data processing internal communications system having plural time-shared intercommunication buses and inter-bus communication means

Also Published As

Publication number Publication date
DE2920490C2 (de) 1983-05-05
FR2426937B1 (fr) 1986-06-13
GB2021824B (en) 1982-02-10
FR2426937A1 (fr) 1979-12-21
GB2021824A (en) 1979-12-05
DE2920490A1 (de) 1979-11-29
JPS54152928A (en) 1979-12-01
US4205373A (en) 1980-05-27

Similar Documents

Publication Publication Date Title
JPS6250862B2 (en])
US4041472A (en) Data processing internal communications system having plural time-shared intercommunication buses and inter-bus communication means
CA1191641A (en) Processor facilities for integrated packet and voice switching
US4695952A (en) Dual redundant bus interface circuit architecture
US4538224A (en) Direct memory access peripheral unit controller
USRE40467E1 (en) Method and apparatus for managing the flow of data within a switching device
US4942552A (en) Method and apparatus for saving and performing industrial control commands
JPS59501436A (ja) 多重化されたフア−スト・イン・フア−スト・アウト・キユ−
US5148527A (en) Interface for independently establishing a link and transmitting high level commands including logical addresses from dedicated microprocessor to shared intelligent memory
CN116483259A (zh) 一种数据处理方法以及相关装置
US4922416A (en) Interface device end message storing with register and interrupt service registers for directing segmented message transfer between intelligent switch and microcomputer
US5113502A (en) Method and apparatus for saving and performing industrial control commands
KR100460108B1 (ko) 듀얼 포트 메모리를 이용한 프로세서의 제어코드 운용방법
US5311510A (en) Data storing system for a communication control circuit
CA1270960A (en) Non coded information and companion data switching mechanism
KR20010053612A (ko) 기억 장치 및 상기 기억 장치를 동작시키기 위한 방법
US5163049A (en) Method for assuring data-string-consistency independent of software
US6112229A (en) Secure terminal and method of communicating messages among processing systems internal thereto
US4630197A (en) Anti-mutilation circuit for protecting dynamic memory
JP3137197B2 (ja) マルチプロセッサシステム
KR100250465B1 (ko) 고속병렬컴퓨터의 메시지 전송 방법
US6741602B1 (en) Work queue alias system and method allowing fabric management packets on all ports of a cluster adapter
JP2505298B2 (ja) スプリットバスにおける可変バス幅指定方式及び可変バス幅情報受信方式
JPH064401A (ja) メモリアクセス回路
JPH0323026B2 (en])